Op Amps · Interactive

DAC/ADC Builder

Build a weighted-resistor DAC, then wrap a comparator, a counter and a register around it to make the staircase and successive-approximation ADCs.

Alt + Shift + P toggles · Esc exits

Build Stage

Each stage adds parts around the same DAC. The filled stages are the ones built so far; the dashed ones are still to come.

DAC Setup

Tick a bit to close its switch: 1 puts Vref on its resistor, 0 leaves it open.

Bits

The number the bits stand for; sets all the bits at once

Number of bits, n

Step Size

Step size for other numbers of bits

The voltage of a 1; 5 V at the start

DAC

vDAC = −Rf × (VD/RD + VC/RC + VB/RB + VA/RA), a summing amplifier with binary-weighted resistors. R = 10 kΩ.

Weighted-resistor DAC Vref feeds one switch and one resistor for each bit, from A, the least significant bit with the largest resistor, to the most significant bit with 5R. The resistors meet at the summing point S of an inverting op amp with feedback resistor Rf, whose output is vDAC. The op amp's supply pins, above and below it, are at plus and minus (Vmax + 1 V), which is where the full scale is applied: its output reaches plus or minus Vmax. While a positive vi is being converted, Vref is negative, so the output is positive. The bits are in DAC Setup, and the present values are in the sentence under the drawing.

DAC Output

  • vDAC for each digital value (thick steps)
  • Filled dot: the present value
Show every value as a table

About the Model

Why convert?

An instrument's response is usually analog, the size of a continuous signal, but the computer that controls the instrument and acquires its data works in the digital domain, where each bit is a 0 (about 0 V) or a 1 (about 5 V). Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) let the two talk, and an op amp sits at the core of both.

The DAC

The DAC is a summing amplifier whose input resistors are binary-weighted: 5R for the most significant bit, doubling to 40R for the least significant of four. A closed switch puts Vref on its resistor; because the summing point S is a virtual ground, each closed branch carries Vref/Rk, and all of that current flows on through Rf, so vDAC = −RfΣVk/Rk. With Vref = 5 V and Rf = 8R the steps are 1 V, from 0 to −15 V. An open switch carries no current, which is the same as putting 0 V on that resistor.

In DAC Setup you choose the full scale, Vmax. Rf is set so that the largest digital value gives −Vmax, and the op amps' supply is set to ±(Vmax + 1 V), so their outputs reach ±Vmax and no value is clipped. More bits give finer steps over the same range, ΔV = Vmax/(2n − 1): 1 V for 4 bits and 14.7 mV for 10 bits with Vmax = 15 V. The resistor for the least significant bit doubles with every bit added (640R at 8 bits), which is why real converters use an R–2R ladder instead. Real resistors bring another problem: resistors that are off by a few percent make uneven steps, and at more bits the steps can even go backwards.

The ADCs

Both converters compare a guess from the DAC with the analog input, and there is no inverter between them. With Vref positive the DAC's output runs from 0 to −Vmax, which suits a negative vi: vDAC goes to the comparator's + input and vi to its − input. For a positive vi, Vref is made negative, so the output runs from 0 to +Vmax, and the two inputs swap. Either way the comparator, an op amp with no feedback, sits at +Vmax (high) while the guess falls short of vi and flips to −Vmax (low) once the guess reaches it (the input difference passes through about 0).

  • Staircase: while the comparator is high, the gate is open: it passes clock pulses and the counter counts up, 0000, 0001, 0010 and so on. When the guess reaches vi, the comparator goes low, the gate closes and the count is the result: the first value that reaches vi. It can take up to 2n − 1 pulses.
  • Successive approximation: the register starts at 0 and guesses half the range. Too small (comparator high)? Keep that bit and add half of the previous step. Too large (low)? Drop it and add half. Each clock step tries one bit and decides it at once, so every step is a new guess and any input takes the same n steps. The result is the largest value that falls short of vi, so it can differ from the staircase's by one step.

What is simplified

  • Every op amp has gain 105 and no input current, and runs from ±(Vmax + 1 V) with 1 V of headroom, so its output reaches ±Vmax (±15 V at the start). The comparator is the same op amp used open loop.
  • The resistors are exact.
  • A real ADC holds vi steady during a conversion with a sample-and-hold circuit; here, changing vi starts the conversion again.
  • The sign of Vref, and which comparator input gets vDAC, follow the sign of vi at once; a real converter would be built for one polarity, or switch its reference.
  • Clock steps are slowed to a few per second so each one can be followed.

Keyboard

Tab moves between controls; Space ticks a bit; arrow keys move sliders (the Digital value slider steps one value at a time). Clicking a switch on the schematic also toggles its bit. Alt + Shift + P (Option + Shift + P on a Mac) switches presentation mode on and off, and Escape leaves it.